MB15F72UL Datasheet, PDF (9/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F72UL
• Programmable Counter
(LSB)
Data Flow
(MSB)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 LDS ^{SWIF/ FCIF/} A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
RF
RF
A1 to A7
N1 to N11
LDS
SWIF/RF
FCIF/RF
CN1, CN2
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: LD/fout signal select bit
: Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)
: Phase control bit for the phase detector (IF : FCIF, RF : FCRF)
: Control bit
Note : Data input with MSB first.
(2) Data setting
• Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)
Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
3
0
00
0
0 000
0
0
0 011
4
•
•
•
16383
0
00
0
0 000
0
0
0 100
•
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• •••
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1
11
1
1 111
1
1
1 111
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting (N1 to N11)
Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
3
0
0
0
0
0
0
0
0
0
11
4
•
•
•
2047
0
0
0
0
0
0
0
0
1
00
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•
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•
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1
1
1
1
1
1
1
1
1
11
Note : Divide ratio less than 3 is prohibited.
• Binary 7-bit Swallow Counter Data Setting (A1 to A7)
Divide ratio A7 A6 A5 A4 A3 A2 A1
0
0 000000
1
0 000001
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127
1 111111
9