MB15F72UL Datasheet, PDF (12/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F72UL
4. Serial Data Input Timing
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
Data
1st data
MSB
2nd data
Control bit Invalid data
LSB
Clock
t1
t2
t7
LE
t3
t6
t4
t5
Parameter
t1
t2
t3
t4
Min.
20
20
30
30
Typ.




Max. Unit
 ns
 ns
 ns
 ns
Parameter
t5
t6
t7
Min. Typ. Max. Unit
100   ns
20   ns
100   ns
Note : LE should be “L” when the data is transferred into the shift register.
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