MB15F72UL Datasheet, PDF (3/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F72UL
s PIN DESCRIPTION
Pin no.
Pin name I/O
TSSOP BCC
Descriptions
1
19
OSCIN
I
The programmable reference divider input. TCXO should be connected with an
AC coupling capacitor.
2
20 GND  Ground for OSC input buffer and the shift register circuit.
3
1
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
4
2
XfinIF
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3 GNDIF  Ground for the IF-PLL section.
6
4
VCCIF

Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit) , the OSC input buffer and the shift register circuit.
Power saving mode control for the IF-PLL section. This pin must be set at “L”
7
5
PSIF
I when the power supply is started up. (Open is prohibited.)
PSIF = “H” ; Normal mode / PSIF = “L” ; Power saving mode
8
6
VpIF  Power supply voltage input pin for the IF-PLL charge pump.
9
7
DOIF O Charge pump output pin for the IF-PLL section.
Lock detect signal output (LD) /phase comparator monitoring
10
8 LD/fout O output (fout) pins.The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
11
9
DORF O Charge pump output pin for the RF-PLL section.
12 10 VpRF  Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control pin for the RF-PLL section. This pin must be set at
13 11 PSRF I “L” when the power supply is started up. (Open is prohibited.)
PSRF = “H” ; Normal mode / PSRF = “L” ; Power saving mode
14
12
VCCRF

Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit)
15 13 GNDRF  Ground for the RF-PLL section
16
14
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
18 16
LE
I When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
Serial data input pin (with the schmitt trigger circuit)
19
17
Data
I
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
3