MB15F02SL Datasheet, PDF (9/25 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F02SL
Programmable Counter
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1
CN2
LDS
SWIF/
SWRF
FCIF/
FCRF
A1
A2
A3
A4
A5
A6
A7
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
CN1, CN2
N1 to N11
A1 to A7
SWIF/SWRF
FCIF/FCRF
LDS
: Control bit
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)
: Phase control bit for the phase detector (IF: FCIF, RF: FCRF)
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table 1]
[Table 4]
[Table 5]
[Table 6]
[Table 7]
[Table 8]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio
(R)
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
00
0
00
0
011
4
0
0
0
0
0
00
0
00
0
100
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
11
1
11
1
111
Note: Divide ratio less than 3 is prohibited.
Table 3. Test Purpose Bit Setting
T1
T2
LD/fout pin state
L
L
Outputs frIF.
H
L
Outputs frRF.
L
H
Outputs fpIF.
H
H
Outputs fpRF.
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