MB15F02SL Datasheet, PDF (12/25 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F02SL
s SERIAL DATA INPUT TIMING
1st data
Data
MSB
Control bit Invalid data
2nd data
LSB
Clock
t1
t2
t7
LE
t3
t6
t4
t5
On rising edge of the clock, one bit of the data is transfered into the shift register.
Parameter
t1
t2
t3
t4
Min.
20
20
30
30
Typ.
–
–
–
–
Max.
–
–
–
–
Unit
ns
ns
ns
ns
Parameter
t5
t6
t7
Min.
100
20
100
Typ.
–
–
–
Max.
–
–
–
Unit
ns
ns
ns
Note: LE should be “L” when the data is transferred into the shift register.
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