MB85RS256BPNF-G Datasheet, PDF (8/36 Pages) Fujitsu Component Limited. – 256 K (32 K × 8) Bit SPI

MB85RS256B
• RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the
RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising
of CS. RDSR command is applicable to “Up to 33 MHz operation”.
CS
SCK
0 1 2 3 4 5 6 70 1 2 3 4 5 6 7
SI
00000101
SO
High-Z
MSB
Invalid
Data Out
Invalid
LSB
• WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot
be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing
WRSR command, and do not change the WP signal level until the end of command sequence. WRSR
command is applicable to “Up to 33 MHz operation”.
CS
SCK
SI
SO
012345670 1 2 3 4 5 6 7
Instruction
Data In
0000000176543210
MSB
LSB
High-Z
8
DS501-00021-2v0-E