MB85RS256BPNF-G Datasheet, PDF (34/36 Pages) Fujitsu Component Limited. – 256 K (32 K × 8) Bit SPI

MB85RS256B
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
■ FEATURES
1
Revised the Data retention
10 years ( + 85 °C)
→10 years ( + 85 °C), 95 years ( + 55 °C),
over 200 years ( + 35 °C)
10
■ COMMAND
• RDID
Deleted the following description:
“RDID command is applicable to “Up to 33 MHz operation”.”
■ POWER ON/OFF SEQUENCE Revised the following description:
“VDD pin is required to be rising from 0 V because turning the
power on from an intermediate level may cause
malfunctions, when the power is turned on.”
→ “If VDD falls down below 2.0 V, VDDin is required to be started
from 1.0 V or less to prevent malfunctions when the power is
17
turned on again (see the figure below).”
Moved the following description under the table:
“If the device does not operate within the specified conditions of
read cycle, write cycle or power on/off sequence, memory data
can not be guaranteed.”
■ FRAM CHARACTERISTICS Revised the table and Note
18 ^{■ ESD AND LATCH-UP}
Revised the following description:
“occurred” → “occur”
■ RESTRICTED SUBSTANCES Revised the following description:
21
“the below regulations” → “the regulations below”
“as belows” → “as follows”
34
DS501-00021-2v0-E