MB85R256H Datasheet, PDF (8/14 Pages) Fujitsu Component Limited. – Memory FRAM CMOS 256 K (32 K × 8) Bit

MB85R256H
■ TIMING DIAGRAM
1. Read cycle (CE Control)
CE
A14 to A0
OE
I/O7 to I/O0
WE
tPC
tAS
Valid
tPC
Valid
tAH
tOE
High-Z
tCE
: Don't care.
tRC
tCA
tRC
tRP
Valid
“H” level
2. Read cycle (OE Control)
CE
A14 to A0
OE
I/O7 to I/O0
WE
tPC
tAS
Valid
tPC
Valid
tAH
tOE
High-Z
tCE
: Don't care.
tRC
tCA
tRC
tRP
Valid
“H” level
8
tPC
tAH
tAS
Valid
tPC
tOHZ
tHZ
High-Z
tPC
tAH
tAS
Valid
tPC
tOHZ
tHZ
High-Z