MB1519 Datasheet, PDF (7/16 Pages) Fujitsu Component Limited. – DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER

BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
Divide N
N
N
N
N
N
N
N
N
N
N
Ratio 11 10
9
8
7
6
5
4
3
2
1
(N)
16
0
0
0
0
0
0
1
0
0
0
0
17
0
0
0
0
0
0
1
0
0
0
1
⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
2047 1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 16 is prohibited.
Divide ratio (N) range = 16 to 2047
BINARY 7-BIT SWALLOW COUNTER DATA SETTING
Divide A
A
AA
A
A
A
Ratio
7
6
5
4
3
2
1
(A)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅ ⋅⋅ ⋅⋅⋅ ⋅⋅
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
DMY : DUMMY BIT INPUT
This bit is set to low in operation.
REF : DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETTING BIT
H = 512 (fr = 25.0 kHz)
L = 1024 (fr = 12.5 kHz)
FP : OUTPUT OF THE PROGRAMMABLE DIVIDER SETTING BIT
H = fp pin (15 pin) outputs programmable divider output frequency (fp1) of transmit section.
L = fp pin (15 pin) outputs programmable divider output frequency (fp2) of reception section.
FC : PHASE CONTROL BIT OF THE PHASE DETECTOR
Output of charge pump is selected by FC pin.
MB1519
fr > fp
fr = fp
fr < fp
VCO Polarity
FC = H
H
Z
L
(1)
FC = L
L
Z
H
(2)
Note: Z = High-impedance
Depending upon the VCO poratity, FC bit should be set.
VCO Output
Frequency
(1)
(2)
VCO Input Voltage
7