MB1519 Datasheet, PDF (4/16 Pages) Fujitsu Component Limited. – DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER

MB1519
PIN DESCRIPTIONS
Pin No. Pin Name I/O
1
GND
–
2
OSC_IN
I
3
OSC-
O
OUT
4
fin₁
I
5
V_CC1
–
6
fr
O
7
LD1
O
Descriptions
Ground.
Oscillator input pin.
Oscillator output pin.
A crystal is connected between OSC_IN pin and OSC_OUT pin.
Prescaler input pin of transmit section.
The connection with VCO should be AC connection.
Power supply voltage input pin of transmit section.
When power is OFF, latched data of transmit section is cancelled.
Monitor pin for programmable reference divider output.
Lock detect signal output pin of transmit section.
Condition
Lock
Unlock
LD pin output level
H
L
8
V_P1
9
D_O1
10
BS1
11
BS2
12
D_O2
13
V_P2
14
LD2
15
fp
–
Power supply voltage input for charge pump and analog switch of transmit section.
O
Charge pump output pin of transmit section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.
O
Analog switch output pin of transmit section.
Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is con-
nected to this pin.
O
Analog switch output pin of reception section.
Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is con-
nected to this pin.
O
Charge pump output pin of reception section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.
–
Power supply voltage input for charge pump and analog switch of reception section.
O
Lock detect signal output pin of reception section.
Condition
Lock
Unlock
LD pin output level
H
L
O
Monitor pin for programmable divider output.
This pin outputs divided frequency of transmit section or reception section depending upon FP bit set-
ting.
FP bit
H
L
Output
Transmit section (fp1)
Reception section (fp2)
4