MB1519 Datasheet, PDF (6/16 Pages) Fujitsu Component Limited. – DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER

MB1519
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins, Data pin, Clock pin, and LE pin. Programmable divider of transmit section and programmable divider of recep-
tion section are controlled individually.
Serial data of binary data is input into Data pin.
On rising edge of clock shifts one bit of serial data into the shift register. When load enable signal is high, the data stored in the shift register is
transferred to either the latch of transmit section or the latch of reception section depending upon the control bit data setting.
Control data
H
L
Destination of serial data
Latch of transmit section
Latch of reception section
SHIFT REGISTER CONFIGURATION
Control bit
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CR FD F A A A A A A A N NN NN NN N NN N
N E P M C 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11
TF
Y
N1 to N11
A1 to A7
FC
DMY
FP
REF
CNT
: Divide ratio of the programmable counter setting bit (16 to 2047)
: Divide ratio of the swallow counter setting bit (0 to 127)
: Phase control bit of the phase detector
: Dummy bit (sets to low)
: Output of the programmable divider control bit (fp1 or fp2)
: Divide ratio of the reference counter setting bit (512 to 1024)
: Control bit
SERIAL DATA INPUT TIMING
• t₁ , t₂, t₃, t₄, t₅ ≥ 1µs
Data
N11 = MSB N10
N1 A7
REF = LSB C: Control bit
Clock
LE
t₂
t₃
t₄
t₁
t₅
On rising edge of the clock shifts one bit of the data into the shift register.
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