MB1519 Datasheet, PDF (5/16 Pages) Fujitsu Component Limited. – DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER

PIN DESCRIPTIONS (Continued)
MB1519
Pin No. Pin Name I/O
16
V_CC2
–
17
fin₂
I
18
LE
I
19
Data
I
Descriptions
Power supply voltage input pin for reception section, programmable reference divider, shift register,
and crystal oscillator.
When power is OFF, latched data of reception section and reference counter is cancelled.
Prescaler input pin of reception section.
The connection with VCO should be AC conneciton.
Load enable input pin. This pin involves a schmitt trigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch depending on a
control data.
At this moment, charge pump output signal is output from BS pin since internal analog swith becomes
ON.
Serial data input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
The stored data in the shift register is transferred to either transmit section or reception section
depending upon a control data.
Control bit data
H
L
The destination of data
Latch of transmit section
Latch of reception section
20
Clock
I
Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
On rising edge of the clock shifts one bit of data into the shift register.
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
f_VCO = {(M x N) + A} x f_OSC ÷ R (A < N)
f_VCO: Output frequency of external voltage controlled ocillator (VCO)
M: Preset divide ratio of dual modulus prescaler (64)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
f_OSC: Reference oscillator frequency
R: Preset divide ratio of reference counter (512 or 1024)
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