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MB1504 Datasheet, PDF (7/19 Pages) Fujitsu Component Limited. – ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER
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SERIAL DATA INPUT TIMING
MB1504
MB1504H
MB1504L
Data S18=MSB S17
*(SW) (S14)
Clock
S10 S9
(S8) (S7)
S1=LSB C: Control bit
(S1)
(C: Control bit)
LE
t1
t2
t1 – t5 ≥ 1µs
t3
t4
t5
On the rising edge of the clock, one bit of the data shifts into the shift registers.
Data in ( ) is used for setting the divide ratio of the programmable reference divider.
PHASE CHARACTERISTICS
VCO CHARACTERISTICS
The FC pin (pin 12) is provided to inverse the phase comparator characteristics.
The characteristics of the internal charge pump output (DO), and phase detector
outputs (ØR, ØP) can be inversed depending upon the FC input data. Outputs
are shown below.
1
FC=H (or open)
DO
ØR
ØP
FC=L
DO
ØR
ØP
fr>fp
H
L
L
L
H
Z
fr<fp
L
H
Z
H
L
L
fr=fp
Z
L
Z
Z
L
Z
Note: Z=(High impedance)
Depending upon VCO characteristics, FC pin should be set accordingly:
When VCO characteristics are like 1 , FC should be set high or open circuit;
When VCO characteristics are like 2 , FC should be set Low.
2
VCO INPUT VOLTAGE
7
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