MB1504 Datasheet, PDF (5/19 Pages) Fujitsu Component Limited. – ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
MB1504
MB1504H
MB1504L
Serial data input is input using the Data pin, Clock pin and LE pin. The 15-bit programmable reference divider and 18-bit programmable divider are
controlled, respectively.
On rising edge of the clock, one bit of the data shifts into the internal shift registers.
When load enable (LE) is high level (or open), data stored in the shift registers is transferred to the 15-bit latch or 18-bit latch depending upon the control bit
level.
Control data “H” : Data is transferred into the 15-bit latch.
Control data “L” : Data is transferred into the 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
The programmable reference divider consists of a 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below.
Last data input
Control bit
LSB
Data input
Divide ratio of prescaler setting bit
MSB
First data input
SSSSSSSSSSSSSS
C
SW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Divide ratio of programmable reference counter setting bits
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide _{S S S S S S S S S S S S S S}
ratio
R
14 13 12 11 10 9 8 7 6 5 4 3 2 1
8
0 00 0 0 0 0 0 0 0 1 0 0 0
9
00000000001001
•
••••••••••••••
16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Divide ratio less than 8 is prohibited
Divide ratio R: 8 to 16383
SW: Divide ratio of prescaler setting bit
SW=“H”: 32
SW=“L” : 64
S₁ to S₁₄: Divide ratio of programmable reference counter setting bits (8 to 16383)
C: Control bit (control bit is set to high)
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