MB1504 Datasheet, PDF (4/19 Pages) Fujitsu Component Limited. – ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER

MB1504
MB1504H
MB1504L
PIN DESCRIPTIONS
Pin No. Pin Name I/O
Descriptions
1
OSC_IN
I Oscillator input
2
OSC_OUT O Oscillator output
A crystal is placed between OSC_IN and OSC_OUT.
3
V_P
— Power supply input for charge pump
4
V_CC
— Power supply voltage input
Charge pump output
5
D_O
O _{The phase characteristics can be inversed depending upon the FC input.}
6
GND
— Ground
Phase comparator output
7
LD
O This pin outputs high when the phase is locked. While the phase difference of f_r and f_p exists, the output
level goes low.
Prescaler input
8
f_IN
I _{The connection with an external VCO should be an AC connection.}
9
Clock
I
Clock input for 19-bit shift register and 16-bit shift register
Each rising edge of the clock shifts one bit of data into the shift registers.
Serial data of binary code input
The last bit of the data is a control bit. The last data bit specifies which latch is activated.
10
Data
I _{When the last bit is high level and LE is high-level, data is transferred to the 15-bit latch.}
When the last bit is low level and LE is high level, data is transferred to the 18-bit latch.
Load enable input (with internal pull up resistor)
11
LE
I When LE is high level (or open), data stored in the shift register is transferred to the latch depending on the
control data.
12
FC
O
Phase selecting input of phase comparator (with internal pull up resistor)
When FC is low level, the charge pump and phase detector characteristics can be inversed.
13
f_r
O
Monitor pin of phase comparator input
It is the same as the programmable reference divider output.
Monitor pin of phase comparator input
14
f_P
O _{It is the same as the programmable divider output.}
15
ØP
O Outputs for external charge pump
16
ØR
O The phase characteristics can be inversed depending on the FC input.
The ØP pin is an N-channel open-drain output.
4