MB1504 Datasheet, PDF (6/19 Pages) Fujitsu Component Limited. – ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER

MB1504
MB1504H
MB1504L
FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown below.
Last data input
Control bit
LSB
Data input
MSB
First data input
SSSSSSSSSSSSSSSSSS
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Divide ratio of swallow counter
setting bits
Divide ratio of programmable counter
setting bits
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide
ratio
A
SSSSSSS
7654321
0
0000000
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide _{S S S S S S S S S S S}
ratio
N
18 17 16 15 14 13 12 11 10 9 8
16
00000010000
1
0000001
17
00000010001
•
•••••••
•
•••••••••••
63
0111111
2047
11111111111
Divide ratio A : 0 to 63
Divide ratio less than 16 is prohibited
Divide ratio N : 16 to 2047
S₈ to S₁₈ : Divide ratio of programmable counter setting bits (16 to 2047)
S₁ to S₇ : Divide ratio of swallow counter setting bits (0 to 127)
C: Control bit (control bit is set to low)
Data is input from the MSB.
6