MB1503 Datasheet, PDF (7/15 Pages) Fujitsu Component Limited. – LOW-POWER PLL FREQUENCY SYNTHESIZER WITH POWER SAVE FUNCTION (1.1GHz)

MB1503
• 7-bit swallow counter divide ratio
• 11-bit programmable counter divide ratio
Divide _{S S S S S S S}
ratio
A
7654321
0
0000000
Divide _{S S S S S S S S S S S}
ratio
N
18 17 16 15 14 13 12 11 10 9 8
16
00000010000
1
0000001
17
00000010001
•
•••••••
•
•••••••••••
127 1 1 1 1 1 1 1
(Divide ratio = 0 to 127)
2047
11111111111
(Divide ratio = 16 to 2,047)
Notes: 1. Divide ratios less than 16 are prohibited for the 11–bit programmable counter
2. S1 to S7: These bits select the divide ratio of the swallow counter (0 to 127)
3. S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047)
4. C: Control bit: (Set low)
5. Input MSB data first
Serial data input timing
• t₁ (≥ 1µs) : Data setup time
t₂ (≥ 1µs) : Data hold time
t₄ (≥ 1µs) : LE setup time to the rising edge of last clock
t₃ (≥ 1µs) : Clock pulse width
t₅ (≥ 1µs) : LE pulse width
Data
S18 =
MSB
S17
(SW) (∗1) (S14)
Clock
S10 S9
(S8)
(S7)
S1 =
LSB
C: Control bit
(S1) (C: Control bit)
LE
t₁
t₂
t₃
t₄
t₅
∗1 : Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.
Note: One bit of data is shifted into the shift register on the rising edge of the clock.
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