MB1503 Datasheet, PDF (6/15 Pages) Fujitsu Component Limited. – LOW-POWER PLL FREQUENCY SYNTHESIZER WITH POWER SAVE FUNCTION (1.1GHz)

MB1503
• 14-bit programmable reference counter divide ratio
Divide ratio S S S S S S S S S S S S S S
R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Divide ratio = 8 to 16,383)
Notes: 1. Divide ratios less than 8 are prohibited
2. SW: This bit selects the divide ratio of the prescaler
SW Low: 128 or 129 (SW must be always be low)
3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383)
4. C: Control bit: Set high
5. Input MSB data first
(b) Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and 11-bit programmable
counter. The serial 19-bit data format is shown below:
Control bit
LSB
Direction of data shift
MSB
SSSSSSSSSSSSSSSSSS
C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Divide ratio setting bit for
swallow counter
Divide ratio setting bit for programmable counter
6