MB1503 Datasheet, PDF (5/15 Pages) Fujitsu Component Limited. – LOW-POWER PLL FREQUENCY SYNTHESIZER WITH POWER SAVE FUNCTION (1.1GHz)

FUNCTIONAL DESCRIPTIONS
MB1503
Pulse swallow function
The divide ratio can be calculated using the following equation:
f_VCO = [(M x N) + A] x f_OSC ÷ R (A < N)
f_VCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 11-bit programmable counter (16 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
f_OSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383)
M : Preset divide ratio of modules prescaler (128)
Serial data input
Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is input to the Data pin.
One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:
Control data
H
L
Destination of serial data
15-bit latch
18-bit latch
(a) Programmable reference divider ratio
The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The serial 16-bit data format is
shown below:
Control bit
LSB
Direction of data shift
Divide ratio setting bit for prescaler
MSB
SSSSSSSSSSSSSS
C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SW
Divide ratio setting bit for programmable reference counter
5