MB86292 Datasheet, PDF (6/25 Pages) Fujitsu Component Limited. – Graphics Display Controller

MB86292
Notes : • The host interface transfers data signals at a fixed width of 32 bits.
• There are 23 lines for address signals handled in double words (32 bits) and 32 Mbytes of address space.
• The external bus can be used at an operating frequency of 100 MHz maximum.
• The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level
sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output signal synchronized to the
rise of BCLKI.
• The host interface supports DMA transfer using an external DMA controller.
• The host interface generates a host processor interrupt signal.
• The RESET pin requires low level input of at least 300 µs after setting "S" (PLL reset signal) to high level.
• Fix the TEST signal at high level.
• In the V832 mode, connect the following pins as specified :
ORCHID Pin Name
V832 Signal Name
A24
MWR
DTACK
TC
DRACK
DMAAK
• Video Output Interface Pins
Pin Name Input/output
Function
DCLKO
Output Display dot clock signal output
DCLKI
Input
Dot clock signal input
HSYNC
Input/output
Horizontal sync signal output
Horizontal sync signal input in external synchronization mode
VSYNC
Input/output
Vertical sync signal output
Vertical sync signal input in external synchronization mode
CSYNC
Output Composite sync signal output
DISPE
Output Display effective period signal
GV
Output Graphics/video select signal
R3-R7
Output Digital video (R) signal output
G3-G7
Output Digital video (G) signal output
B3-B7
Output Digital video (B) signal output
RGBEN
Input
RGB2-0 output/memory bus (MD63-55) select signal
Notes : • The video output interface outputs RGB pieces of five-bit display data by default. It can output RGB pieces
of eight-bit display data depending on conditions. R0-2, G0-2, and B0-2 can be output to MD61-MD63,
MD58-MD60, and MD58-MD60, respectively, by fixing RGBEN to 0. When eight-bit RGB output is selected,
only the 32-bit memory bus width mode can be used.
• Using an additional external circuit, the video output interface can generate composite video signals.
• The video output interface can provide display synchronized with external video. The mode for
synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set
dot clock as for normal display.
• The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset.
• The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level
signal to select video.
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