MB86292 Datasheet, PDF (5/25 Pages) Fujitsu Component Limited. – Graphics Display Controller

MB86292
• Host Interface Pins
Pin Name Input/output
Function
MODE0-
MODE2
Input
Host CPU mode/Ready mode select
RESET
Input
Hardware reset
D0-D31
Input/output Host CPU bus data
A2-A24
Input
Host CPU bus address (Connect A24 to MWR in V832 mode.)
BCLKI
Input
Host CPU bus clock
BS
Input
Bus cycle start signal
CS
Input
Chip select signal
RD
Input
Read strobe signal
WE0
Input
D0-D7 write strobe signal
WE1
Input
D8-D15 write strobe signal
WE2
Input
D16-D23 write strobe signal
WE3
Input
D24-D31 write strobe signal
RDY
Output
Tristate
Wait request signal (“0” for wait state with SH3; “1” for wait state with SH4, V832,
or SPARClite)
DREQ
Output DMA request signal (active low with both SH and V832)
DRACK/
DMAAK
Input
DMA request acknowledge signal (Connect this to DMAAK in V832 mode.
Active high with both SH and V832.)
DTACK/TC
Input
DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active high,
V832 = active low)
INT
Output Host CPU interrupt signal (SH = active low, V832 = active high)
TESTH
Input
Test signal
Note : The host interface can connect the MB86292 to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the
V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using
the SRAM interface allows the MB86292 to use another CPU.) The host CPU is set by the MODE0 and
MODE1 pins as shown below.
MODE1 pin
L
L
H
H
MODE0 pin
L
H
L
H
SH3
SH4
V832
SPARClite
CPU Type
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To
use the MODE2 signal at "H" level, set the software setting to two cycles.
MODE2 pin
L
H
Ready signal mode
Set RDY signal to “Not Ready” level upon completion of bus cycle.
Set RDY signal to “Ready” level upon completion of bus cycle.
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