MB8508S064CF Datasheet, PDF (5/20 Pages) Fujitsu Component Limited. – 8 M X 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM

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MB8508S064CF-100/-100L
s SERIAL-PD INFORMATION
Byte
Function Described
0 Defines Number of Bytes Written into Serial Memory at Module
Manufacture
1 Total Number of Bytes of SPD Memory Device
2 Fundamental Memory Type
3 Number of Row Addresses
4 Number of Column Addresses
5 Number of Module Banks
6 Data Width
7 Data Width (Continuation)
8 Interface Type
9 SDRAM Cycle Time (Highest CAS Latency)
10 SDRAM Access from Clock (Highest CAS Latency)
11 DIMM Configuration Type
12 Refresh Rate/Type
13 Primary SDRAM Width
14 Error Checking SDRAM Width
15 Minimum Clock Delay for Back to Back Random Column
Addresses
16 Burst Lengths Supported
17 Number of Banks on Each SDRAM Device
18 CAS Latency
19 CS Latency
20 Write Latency
21 SDRAM Module Attributes
22 SDRAM Device Attributes
23 SDRAM Cycle Time (2nd. Highest CAS Latency)
24 SDRAM Access from Clock (2nd. Highest CAS Latency)
25 SDRAM Cycle Time (3rd. Highest CAS Latency)
26 SDRAM Access from Clock (3rd. Highest CAS Latency)
27 Precharge to Activate Min. (tRP)
28 Row Activate to Row Activate Min. (tRRD)
29 RAS to CAS Delay Min. (tRCD)
30 Activate to Precharge Minimum Time (tRAS)
31 Module Bank Density
32 to 61 Unused Storage Locations
62 SPD Data Revision Code
63 Checksum for Byte 0 to 62
64 to 98 Manufacturer’s Information: Unused Storage
99 to 125 Vendor Specific Data: Unused Storage
126 Intel Specification Frequency
127 Intel Specification Details for 66 MHZ Support
128+ Unused Storage Locations
128 Byte
256 Byte
SDRAM
12
8
2 bank
64 bit
+0
LVTTL
10 ns
8.5 ns
Non-Parity
Self, Normal
×16
0
1 Cycle
1, 2, 4, 8, Page
4 bank
2, 3
0
0
UN-buffer
*1
15 ns
9 ns
No Support
No Support
30 ns
20 ns
30 ns
60 ns
32 MByte
—
1
*2
—
—
66 MHZ
CL=2, 3
—
Hex Value
-100/100L
80h
08h
04h
0Ch
08h
02h
40h
00h
01h
A0h
85h
00h
80h
10h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
F0h
90h
00h
00h
1Eh
14h
1Eh
3Ch
08h
00h
01h
57h
00h
00h
66h
CFh
—
Note: Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127.
Some or all data stored into Byte 0 to Byte 127 may be broken.
*1. SDRAM Device Attributes
Bit7
TBD
0
Bit6
TBD
0
Bit5
Upper VCC
tolerance
0 = 10%
0
Bit4
Lower VCC
tolerance
0 = 10%
0
Bit3
Supports
Write 1
/Read Burst
1
Bit2
Supports
Precharge
All
1
Bit1
Supports
Auto-
Precharge
1
Bit0
Supports
Early RAS
Precharge
0
*2.Checksum for Bytes 0 to 62
This byte is the checksum for bytes 0 through 62. This byte contains the value of the low 8-bits of the
arithmetic sum of bytes 0 through 62.
5