MB8508S064CF Datasheet, PDF (16/20 Pages) Fujitsu Component Limited. – 8 M X 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM

MB8508S064CF-100/-100L
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3. READ OPERATIONS
CURRENT ADDRESS READ
Internally the SPD contains an address counter that maintains the address of the last data accessed,
incremented by one. Therefore, if the last access (either a read or write operation) was to address(n), the next
read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = “1”,
the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The
master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.
Refer to Fig. 3 for the sequence of address, acknowledge and data transfer.
Fig. 3 – CURRENT ADDRESS READ
S
T
SLAVE
S
A
ADDRESS
T
BUS ACTIVITY : R
O
MASTER
T
P
SDA LINE
BUS ACTIVITY :
SPD
A
C
K
DATA
RANDOM READ
Random Read operations allow the master to access any memory location in a random manner. Prior to issuing
the slave address with the R/W bit = “1”, the master must first perform a “dummy” write operation on the SPD.
The master issues the start condition, and the slave address followed by the word address. After the word
address acknowledge, the master immediately reissues the start condition and the slave address with the R/
W bit = “1”. This will be followed by an acknowledge from the SPD and then by the eight bits of data. The
master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.
Refer to Fig. 4 for the sequence of address, acknowledge and data transfer.
Fig. 4 – RANDOM READ
S
S
T
SLAVE
WORD
T
SLAVE
S
BUS ACTIVITY :
MASTER
A
R
T
ADDRESS
ADDRESS
A
ADDRESS
R
T
T
O
P
SDA LINE
BUS ACTIVITY :
SPD
A
A
C
C
K
K
A
C
K
DATA
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