MB8508S064CF Datasheet, PDF (17/20 Pages) Fujitsu Component Limited. – 8 M X 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM

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MB8508S064CF-100/-100L
SEQUENTIAL READ
Sequential Read can be initiated as either a current address read or random read. The first data are transmitted
as with the other read mode, however, the master now responds with an acknowledge, indicating it requires
additional data. The SPD continues to output data for each acknowledge received. The master terminates this
transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 5 for the
sequence of address, acknowledge and data transfer.
The data output is sequential, with the data from address(n) followed by the data from address(n+1). The
address counter for read operations increments all address bits, allowing the entire memory contents to be
serially read during one operation. At the end of the address space (address 255), the counter “rolls over” to
address0 and the SPD continues to output data for each acknowledge received.
SLAVE
ADDRESS
BUS ACTIVITY :
MASTER
Fig. 5 – SEQUENTIAL READ
A
A
A
C
C
C
K
K
K
SDA LINE
BUS ACTIVITY :
SPD
A
C
K
DATA (n)
DATA (n+1)
DATA (n+2)
S
T
O
P
DATA (n+x)
4. DC CHARACTERISTICS
Parameter
Note Symbol
Condition
Input Leakage Current
Output Leakage Current
Output Low Voltage
Note: *1. Referenced to VSS.
SILI
0 V ≤ VIN ≤ VCC
SILO
0 V ≤ VOUT ≤ VCC
*1
SVOL
IOL = 3.0 mA
Value
Min.
Max.
–10
10
–10
10
—
0.4
Unit
µA
µA
V
17