MB39A214APFT-G-JNERE1 Datasheet, PDF (41/56 Pages) Fujitsu Component Limited. – 2ch DC/DC converter IC with PFM/ PWM synchronous rectification

MB39A214A
Layout
Consider the points listed below and do the layout design.
y Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor
connected with the VCC and VB pins, and GND pin of the switching system parts with switching system
GND (PGND). Connect other GND connection pins with control system GND (AGND), and separate
each GND, and try not to pass the heavy current path through the control system GND (AGND) as much
as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) at
the single point of GND (PGND) directly below IC. Switching system parts are Input capacitor (C_IN),
Switching FET, fly-back diode (SBD), inductor (L) and Output capacitor (C_OUT).
y Connect the switching system parts as much as possible on the surface. Avoid the connection through the
through-hole as much as possible.
y As for GND pins of the switching system parts, provide the through hole at the proximal place, and
connect it with GND of internal layer.
y Pay the most attention to the loop composed of input capacitor (C_IN), switching FET, and fly-back diode
(SBD). Consider parts are disposed mutually to be near for making the current loop as small as possible.
y Place the bootstrap capacitor (C_BST1, C_BST2) proximal to BSTx and LXx pins of IC as much as possible.
y Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current
flows momentary in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.
y Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of
switching FET. Wire the linewidth of about 0.8 mm to be a standard, as short as possible. Take special
care about the line of the DRVLx pin, and wire the line as short as possible.
y By-pass capacitor (C_VCC, C_VB) connected with VCC, and VB should be placed close to the pin as much as
possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal
through-hole.
y Pull the feedback line to be connected to the VOUTx pin of the IC separately from near the output
capacitor pin, whenever possible. Consider the line connected with VOUTx and FBx pins to keep away
from a switching system parts as much as possible because it is sensitive to the noise.
Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to
the FBx pin. In addition, for the internal layer right under the component mounting place, provide the
control system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the
power supply as much as possible.
Consider that the discharge current momentary flows into the VOUTx pin (about 200 mA at Vout = 5 V)
when the DC/DC operation stops, and then sustain the width for the feedback line.
There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and
parts sensitive to noise should be considered to be placed away from the inductor (or backside of place
equipped with inductor).
Layout example of IC peripheral
Layout example of switching system parts
1pin
AGND
AGND
CBST1
CVCC
Through-hole
High-side FET
High-side FET
VIN
CIN CIN
PGND
CVB
Low-side FET
To the LX1 pin
SBD(option)
Output voltage setting
resistor layout
L
CBST2 ^PGND
Connect AGND and PGND right under IC
PGND
COU T
COU T
Low-side FET
To the LX2 pin
SBD (option)
L
VOUT1
VOUT2
Surface
Internal
layer
Output voltage Output voltage
VOUT1 feedback VOUT2 feedback
DS405-00007-1v0-E
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