MB39A214APFT-G-JNERE1 Datasheet, PDF (34/56 Pages) Fujitsu Component Limited. – 2ch DC/DC converter IC with PFM/ PWM synchronous rectification

MB39A214A
If the formula above has been already satisfied and then a low ON resistance FET as possible is used for the
low-side FET, the loss is effectively decreased. Especially, it works dramatically in the low on duty mode.
The loss of the low-side FET can be calculated by the following formula.
P_SyncFET = P_{RON_Sync} = I_{OUT_MAX2} ¯ (1 –
V_{OUT ) ¯ RON_Sync}
V_IN
P_SyncFET : Low-side FET loss [W]
P_{RON_Sync} : Low-side FET conduction loss [W]
I_{OUT_MAX} : Maximum load current [A]
V_IN
: Power supply voltage [V]
V_OUT : Output voltage [V]
R_{ON_Sync} : ON resistance of low-side FET [Ω]
Turn-on and turn-off voltage of the low-side FET is generally small and the switching loss is small enough
to ignore, so that is omitted here.
Especially, when turning on the high-side FET under the high power supply voltage condition, the
rush-current might be generated by according to self-turn-on of the low-side FET. The parasitic capacitor
value of the low-side FET needs to satisfy the following conditions.
V_{TH_Sync} >
C_rss
C_iss
¯V_IN
V_{TH_Sync}
C_rss
C_iss
V_IN
: Threshold voltage of low-side FET [V]
: Parasitic feedback capacitance of low-side FET [F]
: Parasitic input capacitance of low-side FET [F]
: Power supply voltage [V]
Also approaches of adding a capacitor close between the gate source pins of the low-side FET or adding
resistor between the BST pin and the boost capacitor, and so on are effective as a countermeasure of the
self-turn-on(adding resistor between the BST pin and the boost capacitor is also effective to adjust turn-on
time of the high-side FET).
This device monitors the gate voltage of the switching FET and optimizes the dead time. If the dumping
resistor is inserted among DRVH, DRVL and the switching FET gate to adjust turn-on and turn-off time of
the switching FET, this function might malfunction. In this device, resistor should not be connected among
the DRVH pin, the DRVL pin of IC and the switching FET gate, and should be connected by low
impedance as possible.
The gate drive power of the switching FET is supplied from LDO (VB) of IC inside. Select switching FET
so that the total amount of the switching FET electric charge for 2 channels (QG_Total1, QG_Total2)
satisfies the following formula.
I_{VB_MAX} > Q_{G_Total1} ¯ f_OSC1 + Q_{G_Total2} ¯ f_OSC2
I_{VB_MAX}
Q_{G_Total1}
Q_{G_Total2}
f_OSC1
f_OSC2
: VB load current upper limit value (see the following graph) [A]
: Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]
: Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]
: CH1Switching frequency [Hz]
: CH2 Switching frequency [Hz]
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DS405-00007-1v0-E