MB15E03SLPFV1-G-BND-6E1 Datasheet, PDF (25/32 Pages) Fujitsu Component Limited. – Single PLL Frequency Synthesizers with On-Chip Prescalers

Single PLL Frequency Synthesizers with On-Chip Prescalers
Functional Descriptions
Power-Saving Mode (Intermittent Mode Control)
The Intermittent Mode Control circuit greatly reduces the PLL
power consumption by shutting down various internal functions,
depending upon the settings of the power-save (PS) pins. (See the
Electrical Characteristics chart for the specific value of current when
the device is in the power-saving mode.) In this mode, the phase
detector output, Do, becomes high impedance.
Setting the PS pin high releases the power-saving mode, returning
the selected PLL to normal operation.
The intermittent mode control circuit also ensures a smooth startup
when the device returns to normal operation, at which time the phase
comparator output signal is unpredictable due to the unknown
relationship between the comparison frequency (fp) and the reference
frequency (fr). This can cause a major change in the comparator
output, resulting in a VCO frequency jump and an increase in lock-
up time.
To prevent this the Intermittent Mode Control circuit limits the
magnitude of the error signal from the phase detector when it returns
to normal operation.
When power (V_CC) is first applied, the device must be in standby mode, PS = Low, for at least 1µs.
Table 10. Power Save Pin Setting (PS Pins)
PS Pins
H
L
Status
Normal mode
Power saving mode
Power-ON Timing
VCC
Clock
Data
LE
PS
OFF
ON
tV ≥ 1 µS
(1)
(2)
(1) PS = L (power-saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (V_CC > 2.2V).
(3) Release power-saving mode (PS: L → H) 100 ns later after setting serial data.
tPS ≥ 100 nS
(3)
24 Fujitsu Microelectronics, Inc.