MB15E03SLPFV1-G-BND-6E1 Datasheet, PDF (22/32 Pages) Fujitsu Component Limited. – Single PLL Frequency Synthesizers with On-Chip Prescalers

MB15ExxSL Series
Functional Descriptions
Shift Register Configuration
Programmable Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CAAAAAAANNNNNNNNNNN
N
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9 10 11
T
CNT
N1 to N11
A1 to A7
Control bit
Divide ratio setting bits for the programmable counter (3 to 2,047)
Divide ratio setting bits for the swallow counter (0 to 127)
Note: Input data with MSB first.
[Table 1]
[Table 3]
[Table 4]
Table 2. Binary 14-Bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
3
4
.
16383
R
R
R
R
R
R
R
R
R
R
R
R
R
R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-Bit Programmable Counter Data Setting
Divide
ratio
(N)
3
4
.
2047
N
N
N
N
N
N
N
N
N
N
N
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Fujitsu Microelectronics, Inc. 21