MB15E03SLPFV1-G-BND-6E1 Datasheet, PDF (23/32 Pages) Fujitsu Component Limited. – Single PLL Frequency Synthesizers with On-Chip Prescalers

Single PLL Frequency Synthesizers with On-Chip Prescalers
Functional Descriptions
Table 4. Binary 7-Bit Swallow Counter Data Setting
Divide
Ratio
(A)
0
1
.
127
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table 5. Prescaler Data Setting for MB15E03SL, MB15E05SL (SW Bit)
SW
Prescaler Dived Ratio
H
64/65
L
128/129
Prescaler Data Setting for MB15E07SL (SW Bit)
SW
Prescaler Dived Ratio
H
32/33
L
64/65
Relationship Between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (D_O) and the phase
comparator output (fr, fp) are reversed according to the FC bit setting. Also, the monitor pin (f_OUT) output is controlled by the FC bit.
The relationship between the FC bit setting and each of D_O, fr, and fp is shown below.
Table 6. FC Bit Data Setting (LDS =“H”)
FC = High
Do
fR
fP
LD/fout
Do
fr > f_P
H
L
L
L
fr < f_P
L
H
Z*
fout = fr
H
fr = f_P
Z*
L
Z*
Z*
FC = Low
fR
fP
H
Z*
L
L
L
Z*
LD/fout
fout = fp
* High impedance
22 Fujitsu Microelectronics, Inc.