MB85RC64TAPNF-G Datasheet, PDF (20/28 Pages) Fujitsu Component Limited. – 64 K (8 K × 8) Bit I2C

MB85RC64TA
■ NOTE ON USE
• We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
• During the access period from the start condition to the stop condition, keep the level of WP, A0, A1 and
A2 pins to the “H” level or the “L” level.
■ ESD AND LATCH-UP
Test
ESD HBM (Human Body Model)
JESD22-A114 compliant
ESD MM (Machine Model)
JESD22-A115 compliant
ESD CDM (Charged Device Model)
JESD22-C101 compliant
Latch-Up (I-test)
JESD78 compliant
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
Latch-Up (Current Method)
Proprietary method
Latch-Up (C-V Method)
Proprietary method
DUT
MB85RC64TAPNF-G-BDE1
• Current method of Latch-Up Resistance Test
Protection Resistance
Value
≥ |2000 V|
≥ |200 V|
≥ |1000 V|
⎯
⎯
⎯
≥ |200 V|
A
IIN
Test terminal
VDD
+
VIN
V
-
DUT
VSS
Reference
terminal
VDD
(Max.Rating)
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the
latch up does not occur under IIN = ± 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
20
DS501-00044-2v0-E