MB85RC64TAPNF-G Datasheet, PDF (11/28 Pages) Fujitsu Component Limited. – 64 K (8 K × 8) Bit I2C

MB85RC64TA
• High Speed Mode
MB85RC64TA supports High Speed mode up to 3.4 MHz. By sending an entry command (0000 1XXX) after
start condition from the master side, it informs to the slave that the data transmission with High Speed mode
will start.
Since there is no slave side which is allowed to respond to this entry command, NACK response continues
from the slave side. After the master side recognizes this NACK response, the master side changes its state
to High Speed mode and enables the bidirectional communication up to 3.4 MHz.
By sending Stop condition, it exits out of the state in High Speed communication.
Byte Write @High Speed Mode
S 0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A
Write
Data 8bits
AP
Page Write @High Speed Mode
S 0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A
Write
Data 8bits
A
Write
Data
... A P
Current Address Read @High Speed Mode
S 0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
NP
Random Address Read @High Speed Mode
S 0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A S 1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
NP
Sequential Read @High Speed Mode
S 0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A S 1 0 1 0 A2 A1 A0 1 A
... ^Read
Data 8bits
A
...
A
Read
Data 8bits
A
Read
Data
... _A
Read
Data 8bits
NP
Standard Mode
Fast Mode
Fast Mode Plus
High Speed Mode
Access from master
Access from slave
S _{Start Condition}
P _{Stop Condition}
A A _{ACK(SDA is the “L” level)}
N N _{NACK(SDA is the “H” level)}
DS501-00044-2v0-E
11