MB85RC64TAPNF-G Datasheet, PDF (10/28 Pages) Fujitsu Component Limited. – 64 K (8 K × 8) Bit I2C

MB85RC64TA
• Sequential Read
Data can be received continuously following the Device address word (R/W “1” input) after specifying the
address in the same way as for Random Read. If the read reaches the end of address, the internal read
address automatically rolls over to first memory address 0000H and keeps reading.
...
A
Read
Data 8bits
A
Read
Data
... _A
Read
Data 8bits
NP
Access from master
Access from slave
P Stop Condition
A ACK (SDA is the "L" level)
N NACK (SDA is the "H" level)
10
DS501-00044-2v0-E