MB85RC64TAPNF-G Datasheet, PDF (12/28 Pages) Fujitsu Component Limited. – 64 K (8 K × 8) Bit I2C

MB85RC64TA
• Sleep Mode
MB85RC64TA provides Sleep mode which reduces less current consumption than Standby mode, by stoop-
ing the internal regulator circuits. Following sequences enable the Sleep mode transition.
<Transition to Sleep mode>
a) The master sends start condition followed by F8H.
b) After ACK response from slave, the master sends the device address word.
In this device address word, Read/Write code are Don't care.
c) After ACK response from slave, the master re-sends the start condition followed by 86H.
d) The slave moves to Sleep mode after ACK response to the master.
S 1 1 1 1 1 0 0 0 A 1 0 1 0 A2 A1 A0 R/W A S 1 0 0 0 0 1 1 0 A P
Access from master
Access from slave
S ^{Start Condition}
P ^{Stop Condition}
A ^{ACK(SDA is the “L” level)}
Even if the MB85RC64TA stays in the Sleep mode, SDA and SCL signals are monitored. Following sequences
enable the transition to Standby mode after recovery time (tREC) of internal regulator circuits.
<Exit from Sleep mode>
a) The master sends start condition followed by device address word.
In this device address word, Read/Write code are Don't care.
b) At the rising edge of 9th clock from start condition, an internal regulator starts to operate its recovery
sequence.
c) After the recovery time (tREC) passed, standby mode enabled.
After returning to Standby mode, reading and writing are enabled by sending each command starts with start
condition.
Recovery
S 1 0 1 0 A2 A1 A0 R/W X _operation
S 1 0 1 0 A2 A1 A0 R/W A ͐
Start recovery operation
Access from master
Access from slave
S Start Condition
A ACK(SDA is the “L” level)
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DS501-00044-2v0-E