MB85RS256 Datasheet, PDF (2/19 Pages) Fujitsu Component Limited. – Memory FRAM CMOS 256 K (32 K × 8) Bit SPI

MB85RS256
■ PIN ASSIGNMENT
CS
SO
WP
VSS
(TOP VIEW)
1
2
3
4
8
VDD
7
HOLD
6
SCK
5
SI
(FPT-8P-M02)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select
This is an input pin to make chips select. When CS is “H”, device is in deselect (standby)
1
CS status as long as device is not write status internally, and SO becomes High-Z. Other inputs
from pins are ignored for this time. When CS is “L”, device is in select (active) status. CS has
to be “L” before inputting op-code.
Write Protect
3
WP This is a pin to control writing to a status register. When WP is “L”, writing to a status register
is not operated.
Hold
7
HOLD
This pin is used to interrupt serial input/output without making chips deselect. When HOLD
is “L”, hold operation is activated, SO becomes High-Z, SCK and SI become don’t care.
While the hold operation, CS has to be retained “L”.
Serial Clock
6
SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5
SI
Serial Data Input
This is an input pin of serial data. This inputs op-code, address, and writing data.
Serial Data Output
2
SO This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
8
VDD Supply Voltage
4
VSS Ground
2