MB85RS256 Datasheet, PDF (10/19 Pages) Fujitsu Component Limited. – Memory FRAM CMOS 256 K (32 K × 8) Bit SPI

MB85RS256
■ BLOCK PROTECT
Writing protect block is configured by the WRITE command with BP1, BP0 value of the status register.
BP1
BP0
Protected Block
0
0
None
0
1
6000H to 7FFFH (upper 1/4)
1
0
4000H to 7FFFH (upper 1/2)
1
1
0000H to 7FFFH (all)
■ WRITING PROTECT
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN,
WP as shown in the table.
WEL
WPEN
WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
■ HOLD OPERATION
Hold status is retained without aborting a command if HOLD is “L” while CS is “L”. The timing for starting and
ending hold status depends on the SCK to be “H” or “L” when a HOLD pin input is transited as shown in the
diagram below. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care.
And, SO becomes High-Z while reading command (RDSR, READ) . If CS is risen with hold status, a command
is aborted and device is reset.
CS
SCK
HOLD
Hold Condition
Hold Condition
10