MB85RS16N Datasheet, PDF (2/36 Pages) Fujitsu Component Limited. – 16 K (2 K × 8) Bit SPI

MB85RS16N
■ PIN ASSIGNMENT
(TOP VIEW)
CS
1
8
SO
2
7
WP
3
6
GND
4
5
(FPT-8P-M02)
VDD
HOLD
CS 1
SO 2
SCK
SI
WP 3
GND 4
(TOP VIEW)
(LCC-8P-M04)
8 VDD
7 HOLD
6 SCK
5 SI
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select pin
This is an input pin to make chip select. When CS is the “H” level, device is in deselect
1
CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time.
When CS is the “L” level, device is in select (active) status. CS shall be the “L” level be-
fore inputting op-code. The Chip Select pin is pulled up internally to the VDD pin.
Write Protect pin
3
WP
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN. See “■WRITING
PROTECT” for detail.
Hold pin
7
HOLD
This pin is used to interrupt serial input/output without making chip deselect. When
HOLD is the “L” level, hold operation is activated, SO becomes High-Z, and SCK and SI
become don’t care. While the hold operation, CS shall be retained the “L” level.
Serial Clock pin
6
SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5
SI
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
Serial Data Output pin
2
SO This is an output pin of serial data. Reading data of FRAM memory cell array and status
register are output. This is High-Z during standby.
8
VDD Supply Voltage pin
4
GND Ground pin
2
DS501-00030-3v0-E