MB85RC64APNF-G Datasheet, PDF (14/32 Pages) Fujitsu Component Limited. – 64 K (8 K × 8) Bit I2C

MB85RC64A
■ POWER ON/OFF SEQUENCE
If VDD falls down below 2.0V, VDD is required to be started from 0V to prevent malfunctions when the power
is turned on again.
tpd
VDD
tr
tpu
VDD
2.7 V
VIH (Min)
2.7 V
VIH (Min)
1.0 V
VIL (Max)
1.0 V
VIL (Max)
0V
0V
SDA, SCL
SDA, SCL >VDD × 0.8 ^*
* : SDA, SCL (Max) < VDD + 0.5 V
SDA, SCL : Don't care SDA, SCL >VDD × 0.8 ^* SDA, SCL
Parameter
SDA, SCL level hold time during power down
SDA, SCL level hold time during power up
Power supply rising time
Symbol
tpd
tpu
tr
Value
Unit
Min
Max
85
⎯
ns
85
⎯
ns
10
⎯
μs
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
■ FRAM CHARACTERISTICS
Item
Min
Max
Unit
Parameter
Read/Write Endurance*¹ 10¹²
⎯ Times/byte Operation Ambient Temperature TA = + 85 °C
10
⎯
Operation Ambient Temperature TA = + 85 °C
Data Retention*²
95
⎯
Years Operation Ambient Temperature TA = + 55 °C
≥ 200
⎯
Operation Ambient Temperature TA = + 35 °C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2 : Minimun values define retention time of the first reading/writing data right after shipment, and these values
are calculated by qualification results.
■ NOTE ON USE
• Data written before performing IR reflow is not guaranteed after IR reflow.
• During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and
A2 pins to the “H” level or the “L” level.
14
DS501-00019-2v0-E