MB15C03 Datasheet, PDF (13/24 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip prescaler

MB15C03
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is
set to 1.
Table.3 Divide ratio for the programmable reference divider
Divide
ratio
(R)
5
6
•
16383
RRRRRRRRRRRRRR
0
1
2
3
4
5
6
7
8
9 10 11 12 13
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Less than 5 is prohibited.
(5) Setting data input timing
The MB15C03 uses 20 bits of serial data for the programmable divider and 16 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial
data bits are effective.
To set the divide ratio for the MB15C03 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t1 (≥ 0.5 µs): Data setup time
t2 (≥ 0 5 µs): Data hold time
t4 (≥ 0.5 µs): LE setup time to the rising edge of last clock
t3 (≥ 0.5 µs): Clock pulse width
t5 (≥ 0.5 µs): LE pulse width
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