MB15C03 Datasheet, PDF (11/24 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip prescaler

MB15C03
3. Setting the Divide Ratio
(1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of control bits and divide ratio
setting data. The contorl bits select the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits (6 bits for the swallow counter and 12 bits
for the programmable counter) and control bits as shown in Figure 3.1. In case of the programmable reference
divider, the serial data consists of 14 bits and 2 control bits as shown in Figure 3.2.
The control bits are set to:
C0 = C1= 0
for the programmable divider
C0 = 0, C1 = 1 for the programmable reference divider.
Figure 3 Serial data format
LSB
Direction of data input
MSB
CCAAAAAANNNNNNNNNNNN
0 1 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11
(=0) (=0)
Swallow counter
Programmable counter
Control bit
Figure 3.1 Divide ratio for the programmable divider
LSB
Direction of data input
MSB
CCRRRRRRRRRRRRRR
0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13
(=0) (=1)
Programmable reference counter
Control bit
Figure 3.2 Divide ratio for the programmable reference divider
(2) The flow of serial data
Serial data is received via data pin in synchronization with the clock input and loaded into shift register which
contains the divide ratio setting data and into the control register which contains the control bit. The logical
product (through the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the
enable input of the latches. Accordingly, when LE is set high, the latch for the divider identitied by the control bit
is enabled and the divide ratio data from the shift register is loaded into the selected counter(s).
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