MB15C03 Datasheet, PDF (12/24 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip prescaler

MB15C03
Figure 4 The flow of serial data
Data
Clock
LE
AND
C*
AND
Prescaler
14-bit binary programmable reference counter
Programmable
reference divider
14
14-bit latch
14
18-bit shift register
18
18-bit latch
6
12
6-bit binary swallow counter 12-bit binary programmable
counter
Programmable
divider
* : Control register
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table.2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of
Table.2.2 represent the divide ratio of programmable counter. The control bit is set to 0.
Table. 2 Divide ratio for the programmable divider
Table.2.1 Swallow counter divider A
Table.2.2 Programmable counter divider N
Divide
ratio
(A)
A
0
A
1
A
2
A
3
A
4
A
5
0
000000
1
100000
•
••••••
63 1 1 1 1 1 1
Divide
ratio
(N)
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
NNN
9 10 11
5
101000000000
6
011000000000
•
••••••••••••
4095 1 1 1 1 1 1 1 1 1 1 1 1
Note: Less than 5 is prohibited.
12