MB8508S064CE-100 Datasheet, PDF (12/20 Pages) Fujitsu Component Limited. – 8 M x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM

MB8508S064CE-100/-100L
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(3) CLOCK COUNT FORMULA (*9)
Base Value
Clock ≥ _{Clock Period} ^{(Round off a whole number)}
(4) LATENCY (The latency values on these parameters are fixed regardless of clock period.)
No.
Parameter
1 CKE to Clock Disable
2 DQM to Output in High-Z
3 DQM to Input Data Delay
4 Last Output to Write Command Delay
5 Write Command to Input Data Delay
6 Precharge to Output in High-Z Delay
7 Burst Stop Command to Output in High-Z Delay
8 CAS to CAS Delay (min)
9 CAS Bank Delay (min)
CL = 3
CL = 2
CL = 3
CL = 2
Symbol
ICKE
IDQZ
IDQD
IOWD
IDWD
IROH3
IROH2
IBSH3
IBSH2
ICCD
ICBD
MB8508S064CE
-100/100L
1
2
0
2
0
3
2
3
2
1
1
Unit
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Notes: *1. An initial pause (DESL on NOP) of 200 µs is required after power-up followed by a minimum of eight
Auto-refresh cycles.
*2. 1.4 V or VREF is the reference level for measuring timing of signals.
Transition times are measured between VIH (min) and VIL (max).
*3. AC characteristics assume tT = 1 ns and 50 pF of capacitive load.
*4. Maximum value of CL = 2 depends on tCK.
*5. tAC also specifies the access time at burst mode except for first access.
*6. Specified where output buffer is no longer driven. tOH, tLZ, and tHZ define the times at which the output
level achieves ±200 mV.
*7. Actual clock count of tRC (IRC) will be sum of clock count of tRAS (IRAS) and tRP (IRP).
*8. Operation within the tRCD (min) ensures that access time is determined by tRCD (min) + tAC (max); if tRCD
is greater than the specified tRCD (min), access time is determined by tAC.
*9. All base values are measured from the clock edge at the command input to the clock edge for the next
command input.
All clock counts are calculated by a simple formula:
clock count equals base value divided by clock period (round off to a whole number).
*Source: See MB81F64842C Data Sheet for details on the electrical.
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