e421371 Datasheet, PDF (3/29 Pages) Fuji Electric – Fractional-N PLL Frequency Synthesizer

MB15F83UL
s PIN DESCRIPTION
Pin no.
TSSOP BCC
Pin
name
I/O
Descriptions
1
19
OSCIN
I
The programmable reference divider input pin. TCXO should be connected with
an AC coupling capacitor.
2
20 GND  Ground pin for OSC input buffer and the shift register circuit.
3
1
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
4
2
XfinIF
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3 GNDIF  Ground pin for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section (except for the charge
6
4 VCCIF  pump circuit) , the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
Power saving mode control signal pin for the IF-PLL section. This pin must be set
7
5 PSIF I at “L” when the power supply is started up. (Open is prohibited.)
PSIF = “H”; Normal mode / PSIF = “L”; Power saving mode
8
6
VpIF  Power supply voltage input pin for the IF-PLL charge pump.
9
7
DoIF
O
Charge pump output pin for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Look detect signal output (LD) /phase comparator monitoring output (fout) pins.
10
8 LD/fout O The output signal is selected by an LDS bit in a serial data.
LDS bit = “H”; outputs fout signal / LDS bit = “L”; outputs LD signal
11
9
DoRF
O
Charge pump output pin for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
12
10 VpRF  Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control pin for the RF-PLL section. This pin must be set at
13
11 PSRF I “L” when the power supply is started up. (Open is prohibited. )
PSRF = “H”; Normal mode / PSRF = “L”; Power saving mode
14
12
VCCRF

Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit) .
15
13 GNDRF  Ground pin for the RF-PLL section.
16
14
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be AC coupling.
Load enable signal input pin (with the schmitt trigger circuit.)
18
16
LE
I On a rising edge of load enable, data in the shift register is transferred to the cor-
responding latch according to the control bit in a serial data.
Serial data input pin (with the schmitt trigger circuit.)
19
17 Data I A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
3