e421371 Datasheet, PDF (15/29 Pages) Fuji Electric – Fractional-N PLL Frequency Synthesizer

MB15F83UL
s PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DOIF/RF
Z
L
(FC bit = Low)
H
DOIF/RF
Z
L
LD Output Logic Table
IF-PLL section
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
Unlocking state
RF-PLL section
Locking state/Power saving state
Unlocking state
Locking state/Power saving state
Unlocking state
LD output
H
L
L
L
Notes: • Phase error detection range = −2 π to +2 π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU ≥ 2/fosc [s] : i.e. tWU ≥ 153.8 ns when fosc = 13.0 MHz
tWU ≤ 4/fosc [s] : i.e. tWL ≤ 307.7 ns when fosc = 13.0 MHz
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