e421371 Datasheet, PDF (10/29 Pages) Fuji Electric – Fractional-N PLL Frequency Synthesizer

MB15F83UL
• Binary 10-bit Programable Counter Data Setting (NF1 to NF10)
Divide ratio (N) NF10 NF9 NF8 NF7 NF6 NF5 NF4 NF3 NF2 NF1
18
0
0
0
0
0
1
0
0
1
0
19
0
0
0
0
0
1
0
0
1
1


32
0
0
0
0
1
0
0
0
0
0


1023
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 18 is prohibited.
• Binary 4-bit Swallow Counter Data Setting (AF1 to AF4)
Divide ratio (A)
AF4
AF3
AF2
AF1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0





15
1
1
1
1
Note : A < N − 2
• Spurious cancel Bit Setting
Spurious cancel amount
SC1
SC2
Large
0
0
Midium
0
1
Small
1
0
Note : The bits set how much the amount of spurious cancel.
If the Large is selected, a spurious is tended to become small.
• Phase Comparator Phase Switching Data Setting
FCF = High
FCF = Low
DO
DO
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
1
2
Notes : • Z = High-Z
• Depending upon the VCO and LPF polarity, FC bit should be set.
• Charge pump current select Bit Setting
CSF
Current value
1
± 6.0 mA
0
± 1.5 mA
10