e421371 Datasheet, PDF (13/29 Pages) Fuji Electric – Fractional-N PLL Frequency Synthesizer

MB15F83UL
2. Power Saving Mode (Intermittent Mode Control)
• PS Pin Setting
PS pin
H
Normal mode
L
Power saving mode
Status
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters the power saving mode, reducing the current consumption.
See “s ELECTRICAL CHARACTERISTICS” for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is shown in “sPHASE DETECTOR OUTPUT WAVEFORM the LD Output
Logic table.
Setting the PS pin high releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth start-up when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes: •When power (VCC) is first applied, the device must be in standby mode and PS = Low, for at least 1 µs.
•PS pin must be set “L” for Power ON.
VCC
Clock
Data
LE
PS
OFF
ON
tV ≥ 1 µs
(1)
(2)
tPS ≥ 100 ns
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs after power supply remains stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PS : L → H) 100 ns after setting serial data.
13