56F8037 Datasheet, PDF (99/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
6.3.9 Peripheral Clock Enable Register 0 (SIM_PCE0)
The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings
feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use.
When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has
its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock
is shut off. IPBus writes are not possible.
Setting the PCE bit does not guarantee that the peripheral’s clock is running. Enabled peripheral clocks
will still become disabled in Stop mode, unless the peripheral’s Stop Disable control in the SDn register
is set to 1.
Note:
The MSCAN module supports extended power management capabilities, including Sleep,
Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. Refer to
the 56F802x and 56F803x Peripheral Reference Manual for details.
Base + $C 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
CMPB CMPA DAC1 DAC0
ADC
I2C QSCI1 QSCI0 QSPI1 QSPI0
PWM
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0)
6.3.9.1 Comparator B Clock Enable (CMPB)—Bit 15
• 0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled)
• 1 = The clock is enabled to the Comparator B module
6.3.9.2 Comparator A Clock Enable (CMPA)—Bit 14
• 0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled)
• 1 = The clock is enabled to the Comparator A module
6.3.9.3 Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13
• 0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled)
• 1 = The clock is enabled to the DAC1 module
6.3.9.4 Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12
• 0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled)
• 1 = The clock is enabled to the DAC0 module
6.3.9.5 Reserved—Bit 11
This bit field is reserved. It must be set to 0.
6.3.9.6 Analog-to-Digital Converter Clock Enable (ADC)—Bit 10
• 0 = The clock is not provided to the ADC module (the ADC module is disabled)
• 1 = The clock is enabled to the ADC module
56F8037 Data Sheet, Rev. 2
Freescale Semiconductor
99
Preliminary