56F8037 Datasheet, PDF (133/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Reset Values
Add.
Offset
Register Acronym
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0
$0 GPIOB_PUPEN W
PU[15:0]
RS 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R0 0
$1
GPIOB_DATA W
D[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
$2
GPIOB_DDIR W
DD[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
$3 GPIOB_PEREN W
PE[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
$4 GPIOB_IASSRT W
IA[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
$5
GPIOB_IEN
W
IEN[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
$6
GPIOB_IEPOL W
IEPOL[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
IPR[15:0]
$7
GPIOB_IPEND W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
$8
GPIOB_IEDGE W
IES[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R0 0
$9 GPIOB_PPOUTM W
OEN[15:0]
RS 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R0 0
RAW DATA[15:0]
$A GPIOB_RDATA W
RS 0 0 X X X X X X X X X X X X X X
R0 0
$B
GPIOB_DRIVE W
DRIVE[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 Read as 0
W
Reserved
RS
Reset
Figure 8-2 GPIOB Register Map Summary
56F8037 Data Sheet, Rev. 2
Freescale Semiconductor
133
Preliminary