56F8037 Datasheet, PDF (147/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Reset, Stop, Wait, Mode Select, and Interrupt Timing
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note:
All address and data buses described here are internal.
Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing^1,2
Characteristic
Symbol Typical Min Typical Max
Unit
See Figure
Minimum RESET Assertion Duration
t_RA
4T
—
ns
—
Minimum GPIO pin Assertion for Interrupt
t_IW
2T
—
ns
10-6
RESET deassertion to First Address Fetch³
t_RDA
96T_OSC + 64T 97T_OSC + 65T
ns
—
Delay from Interrupt Assertion to Fetch of first
t_IF
—
instruction (exiting Stop)
6T
ns
—
1. In the formulas, T = system clock cycle and T_osc = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At
8MHz (used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the 56F8037 internal reset stretching circuitry to extend this period to 2^21T.
GPIO pin
(Input)
T_IW
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
56F8037 Data Sheet, Rev. 2
Freescale Semiconductor
147
Preliminary