56F8037 Datasheet, PDF (107/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
6.3.14 I/O Short Address Location Register Low (SIM_IOSALO)
See Section 6.3.13 for general information about I/O short address location registers.
Base + $11 15 14 13 12 11 10 9
8
7
6
5
4
3
Read
Write
ISAL[21:6]
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
2
10
1
1
1
Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO)
6.3.14.1 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.3.15 Protection Register (SIM_PROT)
This register provides write protection of selected control fields for safety-critical applications. The
primary purpose is to prevent unsafe conditions due to the unintentional modification of these fields
between the onset of a code runaway and a reset by the COP watchdog. The GPIO and Internal Peripheral
Select Protection (GIPSP) field protects the contents of registers in the SIM and GPIO modules that control
inter-peripheral signal muxing and GPIO configuration. The Peripheral Clock Enable Protection (PCEP)
field protects the SIM registers’ contents, which contain peripheral clock controls. Some peripherals
provide additional safety features. Refer to the 56F802x and 56F803x Peripheral Reference Manual for
details.
Flexibility is provided so that write protection control values may themselves be optionally locked
(write-protected). Protection controls in this register have two bit values which determine the setting of the
control and whether the value is locked. While a protection control remains unlocked, protection can be
disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by
a chip reset, which restores its default non-locked value.
Base + $12 15 14 13 12 11 10 9
8
7
6
5
4
Read
0
0
0
0
0
0
0
0
0
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-17 Protection Register (SIM_PROT)
3
2
PCEP
0
0
6.3.15.1 Reserved—Bits 15–4
This bit field is reserved. Each bit must be set to 0.
1
0
GIPSP
0
0
56F8037 Data Sheet, Rev. 2
Freescale Semiconductor
107
Preliminary