MCIMX27VOP4 Datasheet, PDF (94/118 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
BCLK
WE1
ADDR ^{Last Valid Addr}
CS[x]
WE3
Address V1
WE2
Address V2
WE4
RW
WE11
LBA
WE7
OE
WE12
WE8
EB[y]
WE9
WE10
ECB
WE18
WE18
WE17
WE17
DATA
WE16
V1 V1+2
Halfword Halfword
WE16
V2
V2+2
Halfword Halfword
WE15
WE15
Figure 55. Synchronous Memory Timing Diagram for Two Non-Sequential
Read Accesses: WSC=2, SYNC=1, DOL=0
BCLK
WE1
ADDR Last Valid Addr
CS[x]
WE3
RW
LBA
WE5
WE11
Address V1
WE12
WE2
WE4
WE6
OE
EB[y]
WE9
WE10
ECB
DATA
WE18
WE17
WE14
WE14
WE13
V1
V1+4 V1+8 V1+12
WE13
Figure 56. Synchronous Memory TIming Diagram for Burst
Write Access—BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1
i.MX27 Data Sheet, Advance Information, Rev. 0.1
94
Preliminary—Subject to Change Without Notice
Freescale Semiconductor